Motherboard PCIe 5.0/4.0 Lane Bifurcation & NVMe Bandwidth Planner (2026)

Mainstream desktop CPUs have a fixed number of direct PCIe 5.0 lanes (typically 20 to 28 usable lanes). When motherboard manufacturers include two or three 'CPU-direct' PCIe 5.0 M.2 slots Alongside required USB4 controllers, they wire PCIe switches to borrow 8 lanes from the primary x16 GPU slot whenever those extra M.2 slots are populated.

PCIe 5.0 x8 delivers 31.5 GB/s unidirectional bandwidth—identical to a full PCIe 4.0 x16 slot. Even on PCIe 4.0 x8 (15.75 GB/s), gaming frame rate loss is typically 1% to 3% unless VRAM capacity is exceeded and the game has to stream assets continuously over the PCIe bus.

All chipset-attached M.2 drives, SATA ports, 2.5G/10G Ethernet, and USB ports share a single uplink pipe back to the CPU. On AMD AM5 (B650/X670/X870), that link is PCIe 4.0 x4 (~7.88 GB/s total). If you run two PCIe 4.0 x4 NVMe SSDs on the chipset simultaneously in RAID 0, their combined 14 GB/s speed is capped at ~7.5 GB/s by the CPU-to-chipset link.

PCIe Bifurcation allows the CPU root complex to split a single physical x16 slot into multiple independent logical links (such as four x4 links) with separate device IDs. This allows passive multi-M.2 adapter cards to host up to four NVMe SSDs in one x16 slot without requiring a costly onboard PCIe switch IC.

While PCIe 4.0 x4 has a raw line rate of 64 Gbps (7.877 GB/s after 128b/130b encoding), every PCIe Transaction Layer Packet (TLP) and Data Link Layer Packet (DLLP) adds framing, sequence numbers, and 32-bit LCRC checksums, leaving roughly 7.3 to 7.5 GB/s of net NVMe payload throughput.